Silicon Labs /Series1 /EFR32MG13P /EFR32MG13P732F512IM48 /SMU /PPUPATD1

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Interpret as PPUPATD1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RMU)RMU 0 (RTCC)RTCC 0 (SMU)SMU 0 (TIMER0)TIMER0 0 (TIMER1)TIMER1 0 (TRNG0)TRNG0 0 (USART0)USART0 0 (USART1)USART1 0 (USART2)USART2 0 (WDOG0)WDOG0 0 (WDOG1)WDOG1 0 (WTIMER0)WTIMER0

Description

PPU Privilege Access Type Descriptor 1

Fields

RMU

Reset Management Unit access control bit

RTCC

Real-Time Counter and Calendar access control bit

SMU

Security Management Unit access control bit

TIMER0

Timer 0 access control bit

TIMER1

Timer 1 access control bit

TRNG0

True Random Number Generator 0 access control bit

USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit

USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit

USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit

WDOG0

Watchdog 0 access control bit

WDOG1

Watchdog 1 access control bit

WTIMER0

Wide Timer 0 access control bit

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